The VTVT Group has developed a standard-cell library targeting the TSMC-0.25um, 2.5-volt CMOS process available via MOSIS . The library can be used with Synopsys synthesis tools and the Cadence Silicon Ensemble Place/Route tool. All of the cells can be viewed and edited using the Cadence Virtuoso layout editor. The cell library requires NCSU design kit or other kits that follow MOSIS design rules. Since MOSIS DEEP design rules are used for our cell library, the NCSU design kit has been modifed slightly and is included in our distribution. In this Release 2 of the VTVT Standard Cell library, which was released on November 1, 2003, we made the following addition and modification to the Release 1: - Additional cells. The Release 2 contains 83 cells , compared with 36 in Release 1. Additional modification to the NCSU design rule check file. Now MOSIS's wide-metal rule is implemented.
The users of the Release 1 of the VTVT standard cell library, or those who downloaded the library prior to November 2003, are recommended to update their library by downloading Release 2. The package for our cell library includes: - layouts of primitive cells Synopsys synthesis (.db) and VHDL simulation libraries
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