41. Verilog Comprehensive verilog programming Language Interface (PLI) http://www.mentor.com/germany/eduservices/courses/fpga_pld/059074.cfm

var gMenuControlID=0; var menus_included = 0; var jsPageAuthorMode = 0; var jsSessionPreviewON = 1; var jsDlgLoader = '/germany/eduservices/courses/fpga_pld/loader.cfm'; var jsSiteID = 1; var jsSubSiteID = 984; var kurrentPageID = 43260; document.CS_StaticURL = "http://www.mentor.com/"; document.CS_DynamicURL = "http://www.mentor.com/"; Mentor Graphics in Deutschland Design Areas Embedded Systems C-Based Design Intellectual Property IC Nanometer Design ... Cabling and Harness Products Products by Design Area Products A to Z Home Deutschland ... FPGA/PLD Verilog Comprehensive Add Courses Confirm Schedule Enter Contact Information There are currently no dates scheduled for this class. Request this class in your area! English Version Dauer 4 tage Preis 2,350 EURO Beschreibung Inhalt Verilog im FPGA/ASIC-Design-Flow Teilnehmer Ingenieure, die kurz vor ihrem ersten Verilog-Designprojekt stehen Voraussetzungern Vorkenntnisse in Verilog oder Erfahrungen mit Softwaresprachen sind nicht erforderlich. Die Kursteilnehmer sollten jedoch im Umgang mit dem Computer vertraut sein und Grundkenntnisse in digitalem Hardwaredesign mitbringen. Duration 4 days Pricing 2,350 EURO

42. EETimes.com - Provis Builds Verilog Simulator With Off-the-shelf Parts It should be noted, however, that Z01X! is not fully IEEE compliant because it doesn t support the verilog programming language interface (PLI). http://www.eetimes.com/story/OEG20000620S0076

Advanced Search Newsletters Edit Calendar Print Subscription ... EE Times Provis builds Verilog simulator with off-the-shelf parts Richard Goering Richard Goering EE Times (06/20/2000 3:32 PM EDT) Z01X! runs on clusters of up to eight 64-bit Sun Ultra 60 workstations linked with a high-speed backplane. Users can either buy all of the required hardware from Sun and configure it to Provis' specifications, or purchase a rack-mounted system set up for Z01X! from Rave Computer Associates, a Sun authorized reseller. Rave's setup includes eight Ultra 60s, two Scalable Coherent Interface (SCI) 1.6-Gbyte/second switches, eight SCI interface boards, and cabling, all for less than $100,000. The Ultra 60s are general-purpose workstations that can be used for any other application. Z01X! is an event-driven, compiled-code Verilog simulator that runs at the switch, gate, register-transfer and behavioral levels. "We map very high-speed primitives into hardware, just like an accelerator," said Tom Williams, president of Provis , which was spun off from Zycad, a now-defunct provider of gate-level accelerators, in 1994. As a result, Williams said, gate-level simulation speeds are four times that of a Zycad Paradigm XP accelerator.

43. EETimes.com - Verilog-2001 Language Ready To Roll New features added to the verilog programming interface (VPI), which is part of the PLI, provide improved control over simulation and debugging, http://www.eetimes.com/story/OEG20011018S0085

Advanced Search Newsletters Edit Calendar Print Subscription ... EE Times Verilog-2001 language ready to roll By Richard Goering Richard Goering EE Times (10/18/2001 4:51 PM EDT) Although the IEEE approved Verilog-2001 in March, until now only a handful of people have had access to working versions of the documentation, said Dennis Brophy, chairman of the Accellera standards organization. "Now we have the authenticated version from the IEEE that's ready for the rest of the industry to use," he said. Compared to previous versions of the language, Verilog-2001 promises to let designers work at a higher level of abstraction, and to achieve more timing accuracy for deep-submicron ICs. It also promises better simulation control and improved tool interoperability through an enhanced programming language interface (PLI). While chip designers have yet to get up to speed on Verilog-2001, a few EDA vendors who have been involved in the standard's development are already moving ahead. For example, Cadence Design Systems Inc. has added some Verilog-2001 constructs to its PKS synthesis and NC-Sim simulation tools and will add more based on user demand, a spokesman said. Co-Design Automation Inc. worked in parallel with the Verilog-2001 effort, and its Systemsim simulator supports Verilog-2001, said Simon Davidmann, chief executive officer of Co-Design. Superlog's additional language capabilities are "built on the Verilog-2001 base," he said. Mentor Graphics Corp. has implemented "substantial parts" of Verilog-2001 into ModelSim, said Anne Sanquini, vice president of Mentor's HDL design division.

44. IEEE AND ACCELLERA ANNOUNCE THE APPROVAL OF VERILOG-2001 AS A REVISED IEEE STAND Enhancements in the verilog programming Language Interface (PLI) provide greater simulation control and improved interoperability. http://standards.ieee.org/announcements/verilog2001.html

Design Automation Standards Listing IEEE Standards Online Providing online subscription access to all IEEE Design Automation standards News Room Home IEEE-SA Information -Fast Facts -Trademarks Authors Product Information ... Contacts IEEE and Accellera Announce the Approval of Verilog-2001 as a Revised IEEE Standard Popular Hardware Description Language Adds Behavioral Modeling Support, Improves ASIC Timing, Simulation Control and Interoperability Contact: Georgia Marszalek, Accellera Public Relations Counsel, + 1 650 345 7477, Georgia@ValleyPR.com Karen McCabe, IEEE Marketing Manager, +1 732 562 3824, k.mccabe@ieee.org For Release: Immediate (PISCATAWAY, NJ, 22 October 2001) To improve design accuracy and address the needs of submicron designers, IEEE 1364 or Verilog-2001 adds capabilities for system-level modeling and greater ASIC timing accuracy. Enhancements in the Verilog Programming Language Interface (PLI) provide greater simulation control and improved interoperability. IEEE 1364-2001 improvements include: 1. Behavioral extensions so designers can model at a higher level and create code faster

45. Aldec Inc. - The Design Verification Company - Products - Riviera - Configuratio Verilog Incremental Compilation, ?, ?. verilog programming Interfaces (PLI/VPI), ?, ?. VHDL Programming Language Interface (VHPI), ?, ? http://www.aldec.com/products/riviera/configurations/

PRODUCTS Active-HDL Riviera Overview Configurations ... Configurations Riviera Configurations The following table presents the Riviera suite configurations. A PDF version is available for download. Feature Configuration Riviera Riviera Pro Supported Languages VHDL EDIF 2 SystemVerilog with Assertions Subset PSL (Property Specification Language) OpenVera Assertions Simulation Common Kernel Simulator Mixed VHDL/Verilog Simulation Native-Compile Architecture Verilog Incremental Compilation Verilog Programming Interfaces (PLI/VPI) VHDL Programming Language Interface (VHPI) Value Change Dump (VCD and Extended VCD) Support Custom Stimulus from Aldec Simulation Database Platform Independent Libraries Simulation Model Protection/Library Encryption Library Refresh Optimized Verilog Netlist Simulation Optional Optional Simulation Save and Restore Linux Only Linux Only Debug and Analysis Code Execution Tracing Advanced Breakpoint Management Accelerated Waveform and List Viewer Waveform Compare Multiple Structure Browsers Memory View Watch Window Call Stack Processes View Advanced Dataflow XTrace Profiler (Performance Metrics)

46. Aldec Inc. - The Design Verification Company verilog programming Interfaces (PLI/VPI), ?, ?, ?. VHDL Programming Language Interface (VHPI), ?, ?. Aldec Simulation Database (ASDB) Support, ? http://www.aldec.com/products/active-hdl/configurations/

PRODUCTS Active-HDL Overview Configurations Multimedia Demo ... Active-HDL Configurations Active-HDL Configurations The following table presents the current product configurations for Active-HDL. Aldec also offers a special Active-HDL with Synplify configuration for customers who seek a completely integrated solution. A PDF version is available for download. Feature Configuration Desktop Master Designer Edition Plus Edition Expert Edition Design Management Design Browser Support for multi-design Workspace Design Flow Manager for All FPGA Vendors C-Synthesis Interface Support Source Revision Control Interface Workspace and Design Archiving Design Entry HDL and Text Editor Language Assistant with Templates and Auto-complete State Machine Editor Block Diagram Editor Hierarchy Viewer with Configurations Support Pre-compiled Vendor Libraries Legacy Schematic Design Import Schematic Symbol Import/Export Code Generation Tools Testbench Generation from Waveforms Testbench Generation from State Diagram IP Core Generator

47. Sensors Magazine Online - February 1999 - A Flexible Evaluation Tool For Sensor verilog programming time is minimized since the communication protocol between the microcontroller and In this case, no verilog programming is required. http://www.sensorsmag.com/articles/0299/flex0299/main.shtml

A Flexible Evaluation Tool for Sensor System ASICs download it free through Sensors WorldLink Eric Jacobsen, Motorola, Inc., Imaging Systems Div. A Standard tools can test the ASIC only after the rest of the system design is complete, and even then they do not allow isolation to help determine which component (ASIC or other) is problematic. The only tool typically available to perform ASIC evaluation is expensive back-end test equipment designed to inspect final ASIC products, which almost certainly cannot debug an ASIC once it resides in a product. Because this equipment is used primarily on the ASIC's manufacturing lines, time on it is expensive and limited, making it impractical for engineers who must examine the ASIC carefully to ascertain problems and verify adherence to a customer's specifications. Let's look at the tool's architecture using general examples to explore its design philosophy (which involves establishing flexible and modular hardware platforms that are easily software configurable) and discuss architecture-related details (e.g., communication protocols, system partitioning, and interdevice connectivity) that may not be readily apparent. These discussions should provide a framework that you can use verbatim or apply to the design of another evaluation tool. We'll finish with an example of how the tool can be used to characterize, calibrate, and evaluate a smart sensor module. The Visual Basic and Assembly Language code for these and other examples are available

48. Verilog Project VeriPage Your one stop source for verilog programming Language Interface (PLI) resources. Rajesh Bawankule s Verilog Center http://www.ebroadcast.com.au/dir/Science/Technology/Electronics/Design/Hardware_

SEARCH GUIDE NEWS AUSTRALIAN TV GUIDE DVD RENTALS ... Hardware Description Languages : Verilog Science The A to Z of science is right here. Tools Alternate Verilog FAQ Verilog FAQ: Includes answers to frequently asked questions and lots of links to other useful sites. Asic Tools Web based verilog generation tools for the common tasks such as crc and lfsr. Also contains links of interest to asic designers. ASIC World Verilog tutorial, Digital Electronics tutorial. With Sample questions asked in Interviews. Links to free tools and books. Examples. A Brief Introduction to PLI A brief introduction to Programming Language Interface. Celia's Verilog and EDA Tips, links and resources. Converter from verilog to html A free perl script that converts verilog to html with most things linked. Also creates hierarchies and indexes for your design. Doulos KnowHow - Verilog Models Analog-to-Digital Converter, Shift Register, Simple RAM Model, Universal Asynchronous Receiver (UAR), 8-bit x 8-bit Pipelined Multiplier models. Handbook on Verilog HDL a handbook describing the basics of Verilog including some history and several examples.

49. Electronic Design Welcome Verilog, created by Phil Moorby at Gateway Design Automation in the mid1980s, without resorting to the verilog programming Language Interface (PLI). http://www.elecdesign.com/Articles/ArticleID/10054/10054.html

50. Electronic Design Welcome substantially better compile and runtime performance than with previous point-tool solutions that use the verilog programming Language Interface (PLI). http://www.elecdesign.com/Articles/ArticleID/3488/3488.html

51. FAQs Yes, you can make use of your own VHDL or Verilog as part of the design flow using a Clike language as an alternative to VHDL or verilog programming. http://www.impulsec.com/faq_page.htm

Frequently Asked Questions Q: Can CoDeveloper handle "untimed" C? Yes, CoDeveloper accepts "untimed" C. "Untimed" refers to C code that does not include additional information related to register boundaries, clocks and reset logic. CoDeveloper automatically parallelizes C code, and there is no need to express such parallelism at the level of individual statements or blocks of code. To do this, CoDeveloper analyzes your C code, finds interdependencies and collapses multiple C statements into single instruction stages representing a single clock cycle. This automated creation of parallel hardware can be controlled by the programmer (for size/speed tradeoffs) using compiler pragmas. Q: Does CoDeveloper fully support my selected FPGA? CoDeveloper generates synthesizable HDL outputs that are compatible with most common FPGA device families. For users of Altera and Xilinx devices the tool includes additional, FPGA-specific optimizations to increase performance. CoDeveloper also supports certain types of FPGA-specific hardware interfaces, including Xilinx FSL, OPB, PLB and APU, and Altera's Avalon. Q: Does CoDeveloper require that an embedded processor be used in the FPGA?

52. UW-Eau Claire Catalogue and asynchronous sequential logic analysis and synthesis, finite state machine design, programmable logic and FPGAs, verilog programming for synthesis. http://www.uwec.edu/oakdev/RAR099/catalogues/2004-2005/cs.htm

2004-2005 UNIVERSITY CATALOGUE C S - Computer Science Computer Information Technologies 3 crs (2.5-1). F, Sp. GE-IB No credit toward computer science major or minor. Not applicable for satisfying B.S.-GE-IB requirement in College of Arts and Sciences. Development and application of appropriate processes and tools to access, organize, evaluate, and communicate information using spreadsheets (MS Excel), word processors (MS Word), databases (MS Access), presentation software (MS PowerPoint), and web-based/internet utilities. Appropriate for students seeking a broader or deeper preparation for efficiently using computer information technologies. Introduction to Programming in C++ 3 crs (3-0). F, Sp.

53. CO723: Introduction To The Verilog Hardware Description Language Language provides you with a general overview of verilog programming for hardware design.......The Introduction to the Verilog Hardware http://www.semizone.com/webcast/product?product_id=723

54. TechOnLine - Top 10 Reasons To Use SystemVerilog Sutherland HDL provides expert Verilog HDL, Verilog PLI, SystemVerilog, fault simulation, and the verilog programming Language Interface. http://www.techonline.com/community/tech_group/eda/webcast/27730

TechOnLine Tech Groups EDAnet On-Demand Webcasts ... Log In Your browser cannot currently view TechOnLine Live or On-Demand Webcasts. Top 10 Reasons to Use SystemVerilog Original Broadcast Date: August 25, 2003 Status: Archived Duration: 60 min. Select a Viewing Option: Overview: Ever increasing design size and complexity are stressing current design and verification methodologies. Now, more than ever, there is a pressing need to adopt a design-for-verification (DFV) methodology that couples specification, design and verification. SystemVerilog is the newly ratified Accellera standard and a Hardware Design and Verification Language (HDVL) that enables DFV using a single backward-compatible, efficient language that is extending Verilog. This technical webcast highlights the ten most important new capabilities of SystemVerilog and why you should consider using SystemVerilog to speed the design and verification process in your next project. About Stuart Sutherland: If you have any questions, please email us at webcast@techonline.com

55. Untitled -- Status Of Implementation Of Project Activities An Algebraic Approach to verilog programming The semantics of a hardware description language is usually given in terms of how a simulator should behave. http://www.iist.unu.edu/home/Unuiist/newrh/I/3/11/docs/report_2.html

Executive Summary Top Postgraduate training/teaching activities Status of implementation of project activities Status of implementation of project activities Formal Techniques for Software Development Staff responsible Chris George, Bernhard K. Aichernig Budgetary provision for 2002 USD 60000 Amount expended and obligated in 2002 USD 48804.75 (81%) Project abstract This project covers much of the training activites of the advanced development group at UNU/IIST. It is centred around the technique of using formal (precise, mathematical) methods to develop reliable software, and in particular uses the RAISE method. It consists of a number of sub-projects in which particular software development tasks are undertaken by fellows (trainees) from developing countries. Sub-projects active during 2002 are: Multiscript This sub-project was completed in March 2002 with the delivery of a demonstrator tool. Chris George was responsible, while the actual work was carried out by Ms Myatav Erdenechimeg from the National University of Mongolia under an SSA agreement. Distance learning This sub-project started in October 2002. The aim is to define the content infrastructure of a Web-based Distance Learning System using XML. Components such as program, course, lecture and exercise will be defined in terms of XML schemas, together with tools to support remote, off-line authoring of such components. Chris George is responsible, and Ms Uyanga Sambuu from Mongolia is the fellow. Completion is expected by July 2003.

56. Chip Design Magazine a Verilog testbench for the SoC system bus and a verilog programming Language We used a mixture of Verilog netlists and behavioral models for the http://www.chipdesignmag.com/display.php?articleId=83&issueId=7

57. Resume For Yu Wang Proficient in C, C++, Tcl/Tk and Matlab programming; Proficient in network programming Working knowledge of verilog programming. PROFESSIONAL ACTIVITIES http://www.soe.ucsc.edu/~ywang/resume.html

Yu Wang (Ph.D.) Department of Computer Engineering University of California, Santa Cruz Santa Cruz, CA 95064 Tel:(831) 459-5436 Fax:(831) 459-4829 Email: ywang@cse.ucsc.edu URL: http://www.cse.ucsc.edu/~ywang/ OBJECTIVE A challenging research and development position in the networking industry EDUCATION University of California at Santa Cruz (UCSC), CA. Ph.D. in Computer Engineering, 06/2004. Dissertation: Medium Access Control in Ad Hoc Networks with Omni-directional and Directional Antennas. ( PDF or gzipped postscript Advisor: Prof. J. J. Garcia-Luna-Aceves. M.Sc. in Computer Engineering, 2001. National University of Singapore (NUS), Singapore. M.Eng. in Electrical Engineering, 2000. Thesis: On Quality of Service and Fairness of Medium Access Control in Wireless Ad Hoc Networks. ( PDF or gzipped postscript Advisors: Dr. Brahim Bensaou and Prof. Chi-Chung Ko. Shanghai Jiaotong University (SJTU), Shanghai, China. B.Eng. in Electronic Engineering (major), 1998. B.Sc. in International Accounting (minor), 1998.

58. SystemVerilog a Verilog verification environment (verilog programming Language Interface aka PLI), Enhancements to existing Verilog constructs, to provide tighter http://www.cs.ucr.edu/~ksewell/systemv.htm

What's all the "Buzz" about SystemVerilog? What is SystemVerilog? Analysis Technical Documents Publications / Articles Assignment: " Try to find some good publications that summarize its [SystemVerilog] features and technical details. We may even want to capture some designs using it in the future. " What is System Verilog Emerging fast as a possible IEEE standard, SystemVerilog seeks to extend Verilog-2001 by adding "C++-like" constructs and assertion-based verification to the standard Verilog language. Instead of using higher-level data structures provided by C/C++ in a Verilog verification environment (Verilog Programming Language Interface a.k.a PLI), SystemVerilog seeks to allow a single development environment for those who design hardware at the system level and those who design hardware at the implementation level. From the SystemVerilog Language Reference Manual(LRM): "SystemVerilog 3.0 is built on top of Verilog 2001. SystemVerilog improves the productivity, readability, andreusability of Verilog based code. The language enhancements in SystemVerilog provide more concise hard-waredescriptions, while still providing an easy route with existing tools into current hardware implementationflows. SystemVerilog adds several new constructs to Verilog-2001, including:" — C data types to provide better encapsulation and compactness of code — int, char, typedef, struct, union, enum

59. Verilog Simulator Gains Verification Capabilities: News From Synopsys substantially better compile and runtime performance than with previous point tool solutions that use the verilog programming language interface (PLI). http://www.electronicstalk.com/news/syn/syn112.html

News Story from: Synopsys Edited by the Electronicstalk Editorial Team on 28 September 2001 Verilog simulator gains verification capabilities VCS 6.0.1 is the latest release of the industry's highest performance Verilog simulator from Synopsis. Note: free email newsletter will have read this news the week it was announced. Send us a blank email now to join the circulation VCS 6.0.1 is the latest release of the industry's highest performance Verilog simulator from Synopsis. The new release contains built-in comprehensive coverage analysis, enabling design teams using VCS to determine their verification quality before tapeout. In addition, Synopsys has added VCS DirectC, a new interface to accommodate the use of C/C++ models within a Verilog verification environment. Coverage metrics are an industry-accepted measure of simulation effectiveness. As a standard part of VCS, designers will now have access to comprehensive built-in coverage analysis, including condition, toggle, line and finite-state-machine coverage. Using these capabilities built into the VCS engine, design teams can easily determine the quality or "coverage" of their verification tests.

60. IVivity.com | CONTACT | JOBS AT IVIVITY Experience in complex ASIC verification and/or ASIC design; Must be strong in SystemC (C/C++), Specman and verilog programming; Must possess good http://www.ivivity.com/jobs.cfm

Contact Us Directions to iVivity Careers Why iVivity? ... About Atlanta Below are a list of Job openings at iVivity: (1) Field Applications Engineer - 2 positions (2) VP - Systems Engineer (3) Software Engineer (4) ASIC Principal Engineer ... (10) Technical Marketing Manager - Storage (1) Title: Field Applications Engineer - 2 positions Skills: BSEE with a minimum of 5-7 years experience. Experience with storage embedded software. Familiarity with at least one of the following protocols: iSCSI, SCSI, FCP, FC, or parallel SCSI. Must have strong TCP/IP programming experience at Kernel level. Responsibilities and Requirements: We are currently looking for two Field Application Engineers, to support our East and West Coast Sales teams. The Field Applications Engineer (FAE) will be the primary point of contact and support for iVivity's Sales Reps. This position requires a team player with strong communication skills and proven success working with customers. (2) Title: VP - Systems Engineer Skills: BS in Computer or Electrical Engineering, MS preferred 7-10 years of experience Ideal candidate will be a Software/Firmware engineer with some experience in Hardware design.

A  B  C  D  E  F  G  H  I  J  K  L  M  N  O  P  Q  R  S  T  U  V  W  X  Y  Z

Page 3     41-60 of 92    Back | 1  | 2  | 3  | 4  | 5  | Next 20