21. Berkeley Unified Parallel C (UPC) Project programming model for both shared and distributed memory hardware. Lightweight Runtime and Networking Layers On distributed memory hardware, http://upc.nersc.gov/

Berkeley UPC - Unified Parallel C (A joint project of LBNL and UC Berkeley) Home Downloads Documentation Bugs ... Internal The UPC Language About this UPC program About this UPC program Unified Parallel C ( UPC ) is an extension of the C programming language designed for high performance computing on large-scale parallel machines. The language provides a uniform programming model for both shared and distributed memory hardware. The programmer is presented with a single shared, partitioned address space, where variables may be directly read and written by any processor, but each variable is physically associated with a single processor. UPC uses a Single Program Multiple Data (SPMD) model of computation in which the amount of parallelism is fixed at program startup time, typically with a single thread of execution per processor. In order to express parallelism, UPC extends ISO C 99 with the following constructs: An explicitly parallel execution model A shared address space Synchronization primitives and a memory consistency model Memory management primitives The UPC language evolved from experiences with three other earlier languages that proposed parallel extensions to ISO C 99: AC Split-C , and Parallel C Preprocessor (PCP). UPC is not a superset of these three languages, but rather an attempt to distill the best characteristics of each. UPC combines the programmability advantages of the shared memory programming paradigm and the control over data layout and performance of the message passing programming paradigm.

22. Hardware - From Only4Gurus.com Summary The ability to check memory references against their associated array/buffer feature in the virtual memory hardware of the X86 architecture. http://www.only4gurus.com/v3/showcat.asp?Cat=Hardware

23. Linux: Memory Error Handling memory hardware failures are very hardware implementation are errors that hardware cannot correct. In this case the data in memory is no longer valid http://kerneltrap.org/node/5293

@import "misc/drupal.css"; @import "modules/bookreview/bookreview.css"; Advertise on KernelTrap Forums News Lists ... Site powered by User login Username: Password: Create new account Request new password Navigation create content recent posts Home Linux: Memory Error Handling Posted by Jeremy on Thursday, June 16, 2005 - 05:17 Russ Anderson posted a Request For Comment document on the lkml discussing the development of a common infrastructure for the Linux kernel for dealing with memory errors. He explained that the effort began with work on the ia64 architecture there has been considerable work on recovering from Machine Check Aborts (MCAs) in arch/ia64. One result is that many memory errors encountered by user applications no longer cause a kernel panic. The application is terminated, but linux and other applications keep running. Additional improvements are becoming dependent on mainline linux support. The docment begins by listing the many times of memory failures, including transient errors which return bad data on one read and good data on another, soft errors in which memory has been corrupted but can be rewritten, and hard errors in which the memory storage cell itself has gone bad and can no longer be written to. It then goes on to briefly discuss various methods for handling memory errors broken into two sections, corrected error handling and uncorrected error handling. Finally, the RFC suggests several forms of common infrastruture that could be implemented in the kernel, including page flags used to mark areas in memory that have gone bad and should no longer be used, a /proc interface for tunning the functionality and for communicating with the BIOS/SAL, and "pseudo task switching" to handle non maskable interrupts sent on some architectures to signal memory errors.

24. Ch4-3 95 Box 41 IBM AP-101 Central Processor and memory hardware The final component of the Shuttle s DPS hardware is the mass memory unit (MMU). http://www.hq.nasa.gov/office/pao/History/computers/Ch4-3.html

Computers in Spaceflight: The NASA Experience - Chapter Four - - Computers in the Space Shuttle Avionics System - The DPS hardware configuration ] The DPS hardware in the shuttle avionics system consists of four major components: general-purpose computers, the data bus network, the multifunction cathode ray tube display system, and the mass memory units. Each is a substantial improvement over similar systems in any previous spacecraft. Together, they are a model for future avionics developments. General-Purpose Computers NASA uses five general-purpose computers in the Shuttle. Each one is an IBM AP-101 central processing unit (CPU) coupled with a custom-built input/output processor (IOP). The AP-101 has the same type of registers and architecture used in the IBM System 360 and throughout the 4Pi series . IBM announced the 4Pi in 1966, so by the early 1970s, when Shuttle procurement was complete, the machine had had extensive operational use . The AP-101 version, which is an upgraded AP-1, has since been used in the B-52 and B-1B military aircraft and the F-8 digital fly-by-wire experimental aircraft. The central processor in each case is the same, but the IOP is adapted to the particular application. Although one of the reasons for choosing the AP-101 was its familiar instruction set, some modifications were necessary for the Shuttle version. Since the execution of instructions is dependent on microcode, rather than hardware only, the instruction set could be changed somewhat. Microcode is a set of primitives that can be combined to create new logic paths in the hardware. The AP-101 has room for up to 2,048 microinstructions, 48 bits in length

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27. CST Inc, The DDR Memory Tester Company That Provides Memory Solution Docmemory PC memory Diagnostic is a stand alone program. CST Inc also makes hardware memory testing systems. http://www.simmtester.com/

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28. MIT Alewife Project: Home Page A largescale multiprocessor that integrates both cache-coherent, distributed shared memory and user-level message-passing in a single integrated hardware framework. Papers available. http://www.cag.lcs.mit.edu/alewife/

MIT Alewife Project: Home Page Alewife is a large-scale multiprocessor that integrates both cache-coherent, distributed shared memory and user-level message-passing in a single integrated hardware framework. Each Alewife node consists of a 33 MHz Sparcle integer unit , an off-the-shelf FPU, 64 kbytes of direct-mapped cache, and 4 Mbytes of globally-shared main memory. The nodes communicate via messages on a two-dimensional mesh network. The current implementation scales directly to 512 nodes. A single-chip Communication and Memory Management Unit (CMMU) on each node holds the cache tags and implements the memory coherence protocol by synthesizing messages to other nodes. All of the node components have been fabricated and tested. Currently, there are three working Alewife machines: one 32-processor system and two four-processor systems. We also have complete packaging for a 128-node system that will be populated with Alewife nodes in the near future. (The 32-node system resides in the lower right quarter of the 128-node chassis.) In addition to our hardware efforts, the Alewife group is pursuing a number of software issues, including synchronization, compilation, runtime-systems and operating-systems design. We currently support two languages, C and MUL-T (a multithreaded dialect of scheme with futures).

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34. Upgrading The Palm Zire Memory, Hardware, Or Palm OS Version Not Possible Upgrading the Palm Zire memory, hardware, or Palm OS version not possible. The Palm™ Zire™ handheld has Masked ROM memory that does not allow you to upgrade http://kb.palmone.com/SRVS/CGI-BIN/WEBCGI.EXE?New,Kb=PalmSupportKB,ts=Palm_Exter

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36. Re: Memory --- - Hardware Discussions - FiringSquad Forums Boards , Official Rules and Announcements, Firingsquad hardware But as I have found out this CPU s memory controller will not read them at DDR 400 http://forums.firingsquad.com/firingsquad/board/message?board.id=hardware&messag

37. Affordable Software Reflective Memory From Citrus Controls A high throughput/low latency using COTS hardware and the internal CPU exception mechanism to implement a reflective memory system for control system, distributed, and wireless networked applications. http://citruscontrols.com/

Software Solutions for Reflective Memory Software Solutions for Reflective Memory Reflective Memory allows networked computer systems to share data. If one computer writes into the memory, that data becomes visible almost instantaneously in all other computers. Reflective memory is commonly used for data acquisition and control system applications, automation, telecommunications, test/measurement, defense and distributed computing. Software Reflective Memory provides this service using standard networking components, so that no additional hardware is required. Computers can be connected on a local network, across the Internet, or via 802.11 wireless. Amirus Mirror Memory for Windows Connect up to 32 computers using standard network hardware Configure up to 64Mbytes of system memory for mirroring. ® 4 processors Fault-tolerant design assures network-wide memory consistency Automatic memory synchronization as new computers connect Integrates with any hardware Reflective Memory system Comprehensive set of management, diagnostic, and test utilities.

38. Intel® 5 Volt Boot Block Flash Memory - Hardware Design Support FAQ See Intel® Advanced+ (C3) Boot Block Flash memory Product Overview. hardware The STS (status) pin indicates the WSM status. The designer can just poll http://www.intel.com/design/support/faq/flash/5v_bootblock.htm

US Home Intel Worldwide Where to Buy Contact Us ... Product FAQs How can you tell if the WSM is ready or busy? There are two ways to check whether or not the WSM is ready or busy: Hardware The STS (status) pin indicates the WSM status. The designer can just poll this pin. If it is logic high, the write operation is complete and the WSM is ready for another operation. If it is logic low, then the write operation has not completed, the WSM is busy, and it is not ready to accept another command. Software Bit 7 of the Status Register indicates the status of the WSM. The designer can poll this bit. If it is logic high, the write operation is complete and the WSM is ready for another operation. If it is logic low, then the write operation has not completed, the WSM is busy, and it is not ready to accept another command. What is the definition of the tPHQV spec? How do you unlock the boot block on an 8-Mbit 44 lead PSOP package?

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40. Intel(R) 5 Volt Bulk Erase Flash Memory - Hardware Design Support FAQ hardware Design Support Product FAQs Intel® 5 Bulk Erase Block Flash memory The Bulk Erase Flash memory is not recommended for new designs. http://www.intel.com/design/support/faq/flash/5v_bulk_erase.htm

US Home Intel Worldwide Where to Buy Contact Us ... Product overviews for these components can be found on the Developer web site. A detailed flowchart of the steps involved in the programming cycles for all Flash components is available in the device datasheet Over-programming Bulk Erase Flash memory devices It is not possible to over-program bulk erase flash memory devices. However, over-erasure is a potential problem, so every memory location in a bulk erase device must be programmed to 00h before the device is erased. Are the Bulk Erase Flash memory quick pulse or auto programmable? Can the upper address lines be tied to ground for Bulk Erase devices? Upper address lines cannot be tied to ground for Bulk Erase devices. Doing this would mean the entire array cannot be addressed and therefore will be overwritten when the algorithm is implemented. The part will eventually fail. How does VppL relate to write protection? VppL is specified as 0V to 6.5V. When Vpp is below 6.5V, the device can't be programmed or erased, thereby offering a form of write protection. Why is the Integrated Stop Timer important?

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