101. GATE, A General Architecture For Text Engineering A computer architecture for a broad range of Natural Language Processing tasks, available under the GNU Public License. Abundant documentation, Java class library, webbased demos. http://www.gate.ac.uk/

GATE HOME docs download support science ... acknowledgments We're hiring! GATE-related jobs in Sheffield. CLOSING DATE 15th SEPTEMBER. GATE is one of the most widely used human language processing systems in the world. It is a tool for: scientists performing experiments that involve processing human language; companies developing applications with language processing components; teachers and students of courses about language and language computation. GATE comprises an architecture, framework (or SDK) and graphical development environment, and has been under construction in Sheffield since 1995. The system has been used for many language processing projects; in particular for Information Extraction in many languages. The system supports the full lifecycle of language processing components, from corpus collection and annotation through system evaluation. GATE is funded by the EPSRC , the EU and commercial users. Some projects SEKT (EC); AKT (EPSRC); PrestoSpace (EC); KnowledgeWeb (EC); MMKM (EPSRC); ETCSL (AHRB); MultiFlora (BBSRC);

102. USC's Advanced Computer Architecture Laboratory The Advanced computer architecture Laboratory (ACAL) of USC Information Sciences Institute Despain s research interests include computer architecture, http://www.isi.edu/acal/

Welcome to the Introduction to the Advanced Computer Architecture Laboratory The Advanced Computer Architecture Laboratory (ACAL) of USC Information Sciences Institute (ISI) researches symbolic and numeric computation to produce its own custom processors and systems. Under the direction of Professor Alvin M. Despain, ACAL is a center for the investigation of high performance symbolic and numeric computing. The Laboratory undertakes experimental research in areas such as compiler technology, computer architecture, VLSI design, and computer-aided design tools. Most recently the Laboratory has invented and is investigating the HiDISC (Hiearchical Decoupled Instruction Stream Architecture). The Laboratory is also investigating the feasibility of Quantum Computing through the use of computer simulation. We are investigating the effect errors have on the fidelity of a quantum calculation. These simulations require vast computational resources, and we are currently utilizing both standard workstations as well as supercomputers such as the Cray T3E. About the Director...

103. Home Page Of The VLSI Computer Architecture And Parallel Processing Group At USF Specific areas of research include computer architecture, interconnection networks, ASIC design, VLSI algorithms and architectures, high level synthesis, http://vcapp.csee.usf.edu/

VLSI, Computer Architecture and Parallel Processing (VCAPP) Research Group at USF Home Faculty Students Alumni Department ... Writting Dissertation Welcome to VLSI, Computer Architecture and Parallel Processing(VCAPP) group at the University of South Florida. Five faculty members and about 20 graduate students are active in these areas. Specific areas of research include computer architecture, interconnection networks, ASIC design, VLSI algorithms and architectures, high level synthesis, low power VLSI, logic simulation, parallel processing, VLSI for data compression, image processing, pattern matching and coding theory.For specific information, we welcome you to browse through the individual faculty and students' pages. Last updated on 29th July 2002.

104. Untitled Document Can simulate Motorola's coldfire5204 microprocessor on the instruction level. Useful for laboratory projects in computer architecture. http://hem.passagen.se/coldfire5204/

Products Simulator for coldfire5204 MathText Equation Editor

105. CS3 Computer Architecture The course textbook is Hennessy and Patterson computer architecture A Quantitative Approach, which is available now in its second edition from Thins at KB. http://www.dcs.ed.ac.uk/teaching/cs3/comparch/module-page.html

CS3 Computer Architecture The course textbook is Hennessy and Patterson Computer Architecture: A Quantitative Approach , which is available now in its second edition from Thins at KB. This is a *** book which covers the course material so closely that there are no printed lecture notes for this module . You are strongly advised to obtain a copy of this book. Announcements Please fill out an evaluation questionnaire ( PS PDF )and return it to the ITO. Every comment will be greatly appreciated and will help improve the module for next year. Course materials syllabus (from CS3 Course Handbook) lecture log lecture slides (in Adobe Acrobat and Adobe Postscript formats) tutorial groups Practicals Practical 1 (out 01/02/02, due 5pm 15/02/02) Practical 2 (out 01/03/02, due 5pm 15/03/02) Past exam papers June 1992 June 1993 June 1994 June 1995 ... June 1999 Contacting the teaching team Marcelo Cintra , JCMB room 3419, ext. 505118

106. The Von Neumann Architecture Of Computer Systems Any discussion of computer architectures, of how computers and computer systems are organized, designed, and implemented, inevitably makes reference to the http://www.csupomona.edu/~hnriley/www/VonN.html

The von Neumann Architecture of Computer Systems H. Norton Riley Computer Science Department California State Polytechnic University Pomona, California September, 1987 Any discussion of computer architectures, of how computers and computer systems are organized, designed, and implemented, inevitably makes reference to the "von Neumann architecture" as a basis for comparison. And of course this is so, since virtually every electronic computer ever built has been rooted in this architecture. The name applied to it comes from John von Neumann, who as author of two papers in 1945 [Goldstine and von Neumann 1963, von Neumann 1981] and coauthor of a third paper in 1946 [Burks, et al. 1963] was the first to spell out the requirements for a general purpose electronic computer. The 1946 paper, written with Arthur W. Burks and Hermann H. Goldstine, was titled "Preliminary Discussion of the Logical Design of an Electronic Computing Instrument," and the ideas in it were to have a profound impact on the subsequent development of such machines. Von Neumann's design led eventually to the construction of the EDVAC computer in 1952. However, the first computer of this type to be actually constructed and operated was the Manchester Mark I, designed and built at Manchester University in England [Siewiorek, et al. 1982]. It ran its first program in 1948, executing it out of its 96 word memory. It executed an instruction in 1.2 milliseconds, which must have seemed phenomenal at the time. Using today's popular "MIPS" terminology (millions of instructions per second), it would be rated at .00083 MIPS. By contrast, some current supercomputers are rated at in excess of 1000 MIPS. And yet, these computers, such as the Cray systems and the Control Data Cyber 200 models, are still tied to the von Neumann architecture to a large extent.

107. Cellmatrix Core Page Publications describe an application of their computer architecture to genetic algorithms. Software includes an online circuit simulator. http://www.cellmatrix.com/entryway/entryway/core.html

Challenge: build your own circuit. introduction technology pages user pages ... exit "street signs, Hong Kong " L. Durbeck, 6/87, photograph

108. Computer Architecture History / CPU History -- Mark Smotherman I am indebted to Dr. Fred Brooks, whose love of computer architecture inspired me in class at UNC, Chapel Hill. It was a privilege to also work as a http://www.cs.clemson.edu/~mark/hist.html

Selected Historical Computer Designs Welcome to a gallery of fascinating machine designs! I want to collect here information on historical firsts and on important machines that are relatively unknown and/or are underappreciated. I am indebted to Dr. Fred Brooks, whose love of computer architecture inspired me in class at UNC, Chapel Hill. It was a privilege to also work as a graduate student assistant for him on early drafts of his architecture text, Computer Architecture: Concepts and Evolution . See his text for a complete history of computer designs. Please email me if you have comments, additional references on items in the collection, or suggestions for additional items. The architects behind the machines List of computer architects The machines admired by computer architects List of admired designs Historical essays Architecture Condition codes (under construction) EPIC (explicitly parallel instruction computing) ILP (instruction-level parallelism) Input/output systems ... System calls and protection mechanisms (under construction) Implementation Decoded instruction caches (under construction) Eager execution (under construction) Prediction buffers (under construction) see also ILP above Microprogramming On-line historical resources Manuals Al Kossow's collection of old computer manuals at bitsavers.org (pdf format)

109. ECE 538: Advanced Computer Architecture ECE 538 Advanced computer architecture. Univ of New Mexico, Fall 2004 Textbook Hennessy and Patterson, computer architecture A Quantitative Approach, http://www.eece.unm.edu/~dbader/ece538/

ECE 538: Advanced Computer Architecture Univ of New Mexico, Fall 2004 Tuesday/Thursday 11:00 AM - 12:15 PM, ECE Room 210 Instructor: Dr. David A. Bader (dbader@ece.unm.edu) Office: ECE 230B Office Hours: Tuesday/Thursday 10:00 - 10:45 AM, or by appointment. Textbook: Hennessy and Patterson, Computer Architecture: A Quantitative Approach , Third edition, Morgan Kaufmann Publishers / Elsevier, 2002 Join the class mailing list at http://www.ece.unm.edu/mailman/listinfo/ece538/ Syllabus Homework Set #1 , due 31 Aug. Homework Set #2 , due 16 Sept. Homework Set #3 , due 7 Oct. Homework Set #4 , due 30 Nov. Reading Assignments: G. Amdahl, G. Blaauw, and F Brooks, Jr. " Architecture of the IBM System / 360 ," IBM Journal, April 1964. William J. Dally, Patrick Hanrahan, Mattan Erez, Timothy J. Knight, Francois Labonte, Jung-Ho Ahn, Nuwan Jayasena, Ujval J. Kapasi, Abhishek Das, Jayanth Gummanraju, and Ian Buck. " Merrimac: Supercomputing with Streams ," Supercomputing 2003, Phoenix, AZ, November 2003. Mark R. Thistle and Burton J. Smith, " A Processor Architecture for Horizon Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, Doug Burger, Stephen W. Keckler, and Charles R. Moore, "

110. Anshul Kumar Indian Institute of Technology, Delhi CAD for VLSI, computer architecture http://www.cse.iitd.ernet.in/~anshul

Anshul Kumar Professor Indian Institute of Technology, Delhi Hauz Khas, New Delhi 110 016, India Phone: +91 (11) 26591321 Fax: +91 (11) 26868765, 26581264 Research Courses VDTT Program A New Start-Up

111. NUCAR Northeastern University computer architecture Research Group We pursue research questions in the areas of computer architecture, Performance Evaluation, http://www.ece.neu.edu/info/architecture/nucar.html

The web site for the NUCAR group has moved Please update your links.

112. Parallel Systems Group University of Toronto researchers working on all aspects of parallel systems computer architecture, OSs, compilers, performance evaluation, applications. Home of Hurricane and Tornado OSs, Hector and NUMAchine multiprocessors. http://www.eecg.toronto.edu/parallel/

Parallel Systems Group The Parallel Systems Group comprises of researchers from the University of Toronto working in all aspects of parallel systems, including computer architecture, operating systems, compilers, performance evaluation and applications. Previous projects include the Hector shared memory multiprocessor, and the Hurricane multiprocessor operating system. The group is currently building the NUMAchine multiprocessor, the Tornado operating system, and the Jasmine compiler. Other Resources University of Toronto Resources University of Toronto High Performance Computing Research Center University of Toronto Electrical Engineering Computer Group University of Toronto Department of Computer Science Computing Resources Supercomputing Web pages Parallel I/O archive at Dartmouth This is still a work in progress... Mail suggestions to: kulki or Orran

113. SECOND WORKSHOP ON COMPUTER ARCHITECTURE EVALUATION USING COMMERCIAL WORKLOADS In Proceedings of the 25th Intl. Symp. on computer architecture. 2 http//jhared.east/share/perftools/shade/shade.html. 3 R. Ramakrishnan. http://iacoma.cs.uiuc.edu/caecw99/

SECOND WORKSHOP ON COMPUTER ARCHITECTURE EVALUATION USING COMMERCIAL WORKLOADS Orlando, Florida Sunday, January 10th, 1999 Immediately precedes the Fifth International Symposium on High Performance Computer Architecture (HPCA-5) Sponsored by the IEEE Computer Society Organized by: Russell Clapp, Informix Software rmc@informix.com Ashwini Nanda, IBM TJ Watson Research Center ashwini@watson.ibm.com Josep Torrellas, University of Illinois at Urbana-Champaign torrella@cs.uiuc.edu Building on the positive feedback enjoyed by the First Workshop on Computer Architecture Evaluation using Commercial Workloads , this second workshop will bring together again researchers and practitioners in computer architecture and commercial workloads from industry and academia. In the course of one day, we will discuss work-in-progress that utilizes commercial workloads for the evaluation of computer architectures. By discussing this ongoing research, the workshop will expose participants to the characteristics of commercial workload behavior and provide an understanding of how commercial workloads exercise computer systems. There will be discussions on the difficulties associated with using commercial workloads to drive new computer architecture designs and what can be done to overcome them. The Final Program for the workshop is listed below, followed by an abstract for each talk. A 20-minute time limit will be strictly enforced for each talk, and there will be plenty of time for audience participation. A round table session discussion will be held after the technical presentations. There will be no proceedings for the workshop since we encourage the presentation of work-in-progress and research in early stages. Copies of the foils used by the speakers will be distributed to the attendees.

114. CAECW '00 THIRD WORKSHOP ON computer architecture EVALUATION USING COMMERCIAL WORKLOADS The field of computer architecture grew up in a time when processors were http://iacoma.cs.uiuc.edu/caecw00/

THIRD WORKSHOP ON COMPUTER ARCHITECTURE EVALUATION USING COMMERCIAL WORKLOADS Toulouse, France Sunday, January 9th, 2000 Immediately precedes the Sixth International Symposium on High Performance Computer Architecture (HPCA-6) Sponsored by the IEEE Computer Society Organized by: Russell Clapp, Informix Software rmc@informix.com Ashwini Nanda, IBM TJ Watson Research Center ashwini@watson.ibm.com Josep Torrellas, University of Illinois at Urbana-Champaign torrella@cs.uiuc.edu Building on the positive feedback enjoyed by the First Workshop on Computer Architecture Evaluation using Commercial Workloads and Second Workshop on Computer Architecture Evaluation using Commercial Workloads , this third workshop will again bring together researchers and practitioners in computer architecture and commercial workloads from industry and academia. In the course of one day, we will discuss work-in-progress that utilizes commercial workloads for the evaluation of computer architectures. By discussing this ongoing research, the workshop will expose participants to the characteristics of commercial workload behavior and provide an understanding of how commercial workloads exercise computer systems. There will be discussions on the difficulties associated with using commercial workloads to drive new computer architecture designs and what can be done to overcome them. The Final Program for the workshop is listed below, with an abstract for each talk. There will be plenty of time for audience participation. A panel with a round-table discussion will be held after the technical presentations. There will be no proceedings for the workshop since we encourage the presentation of work-in-progress and research in early stages.

115. »»Computer Architecture Lab Welcome to the computer architecture Laboratory in the Department of Electrical and Computer Engineering at the University of Central Florida. http://cal.ucf.edu/

Home People Research Partners ... Home Contact Information Physical Location : Engineering Bldg. I - Room 410 with additional resources in Room 270 Telephone Lab Director Dr. Ronald F. DeMara Welcome Welcome to the Computer Architecture Laboratory in the Department of Electrical and Computer Engineering at the University of Central Florida . Our research focus is the design and optimization of uniprocessor and parallel computer architectures for applications involving dependable computing, distributed simulation, and artificial intelligence. Technologies utilized include reprogrammable devices, clockless logic, and evolvable hardware. Information regarding the current and previous research projects, faculty and students involved, and publications are available using the top page menu bar and icons below. Please contact us if you would like to request further information, a presentation on our research, or a tour of the facilities and resources available. You can also sign up on our mailing list to receive periodic research updates by e-mail. Computer Architecture Evolvable Hardware System Architecture ... Computing Intelligent Systems Representation Parallel Knowledge Processing Distributed Simulation Networked Simulation Back to Top Home ... webadmin

116. HPCA6 6th High Performance computer architecture Conference Site. http://www.irit.fr/HPCA6/

117. CS 154 - Computer Architecture, Spring 04 computer architecture is driven from the software side by user needs in terms of functionality and performance and from the hardware side by technological http://www.cs.ucsb.edu/~cs154/

CS 154 - Computer Architecture, Spring 04 Announcements: * A note final note: I am a stickler about grade inflation, and I take the guidelines of the university very seriously. I give out very few full A grades, and if you were one of them then it speaks very highly of your ability as a computer scientist. A B Grade is a student that has a very solid understanding of the material, and I would happily write a letter for a B+ student. A C is a solid grade, one that requires a good deal of work, however you are not a master of the material yet. Be assured, no one skates through with a C (at least if you did, you are a better skater than I). You have been a very good class, and I hope I continue to get students that are good as this in the future. * As was announced in class, the final readings were Busses (8.4,8.5) and Superscalar (6.8). * Key to Homework-3 (Midterm 1) can be found here Homework 3 * Solutions to Midterm 2 midterm 2 solutions * To help you study, here is a copy of the midterm 2 * For the final, you are welcome to 2-sides of handwritten notes

118. Conferences And Journals Covering Computer Architecture And Arithmetic Conferences and Journals covering computer architecture, Arithmetic Formal Verification 30th Annual International Symposium on computer architecture http://engr.smu.edu/~seidel/conferences.html

Journals Conferences Conferences and Journals covering Journals Integration, the VLSI journal IEEE Transactions on Computers IEEE Transactions on VLSI Systems IEE Proceedings - Computers and Digital Techniques ... TCS (Theoretical Computer Science) SIAM Journal on Computing Journal of the ACM Journal of Systems Architecture The Journal of Instruction-Level Parallelism ... IPL (Information Processing Letters) Parallel Computing IEEE Concurency Journal of Parallel and Distributed Computing International Journal of High Speed Computing ... Distributed Computing Conferences Name Deadline Objectives Micro 33 Jun.12,2000 Microarchitecture / Instruction-Level Parallelism VLSI 2001 Jul.10,2000 VLSI Design HPCA 7 Jul.10,2000 High Performance Computer Architecture IEEE-ISCAS 2001 Oct.2,2000 Systems of Circuits ARITH-15 Nov.15,2000 IEEE Intl Symp. on Computer Arithmetic ISCA-28 Nov.24,2000 IEEE Intl Symp. on Computer Architecture Dec.1,2000 IEEE Annual Workshop on VLSI TCS 2001 Jan.5,2001 TCS Special Issue on Real Numbers and Computers Euro-Par 2001 Jan.29,2001 European Conference on parallel computing IEICE Transactions on Fundamentals of Electronics, Comunications and Computer Sciences

119. Michael R Hannaford University of Newcastle Object-oriented software engineering, object-oriented programming, computer architecture. http://www.cs.newcastle.edu.au/~mrh/

Michael R Hannaford Deputy Head of School, University of Newcastle Callaghan, NSW 2308, Australia. Phone: +61 2 4921 6075 Fax: +61 2 4921 6929 Email: Michael.Hannaford@newcastle.edu.au Research Interests Grid Computing Distributed Systems Object-Oriented Software Engineering Current and Recent Research Projects The SpeedOS Operating System The Timor Programming Language Software Technology for Agents Course Information COMP2200/COMP6200 Comparative Programming Languages SENG3100/SENG6100 Advanced Software Process COMP3290/COMP6290 Compiler Design SENG3300/SENG6300 User Interface Design

120. ERCB: Computer Architecture: A Quantitative Approach, 2nd Ed. computer architecture A Quantitative Approach is a tourde-force on several levels. It is even more clear now that computer architecture is one of the http://www.ercb.com/brief/brief.0042.html

ERCB Home New Feature Brief ... Links Vital Statistics Title Computer Architecture: A Quantitative Approach: Second Edition Authors Hennessy, John L. and Patterson, David A. Publisher Morgan Kaufman Publishers, Inc. San Francisco, California http://www.mkp.com/ ISBN Pages 760 plus appendices, bibliography, and index Price Rebirth of an Instant Classic When I reviewed the first edition of this book in the October, 1990 Programmer's Bookshelf column of Dr. Dobb's Journal, I wrote: Computer Architecture: A Quantitative Approach is a tour-de-force on several levels. The book is a masterpiece of technical writing Hennessy and Patterson's clear, direct style is absorbing and effective, and their enthusiasm for their subject is contagious. The design and production, too, are impeccable. Furthermore, because the book presents a hardheaded and pragmatic approach to computer design, based on real examples, real measurements, and lessons learned from the successes and misadventures of the past, it should revolutionize the teaching of computer architecture and implementation. Although this book was not written primarily for programmers, it is a thorough and extraordinarily wide-ranging education in that magical interface between the programmer's intentions and the electron's actions. It should be read by every software craftsman who cares about wringing the last drop of performance from his machine.

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